The requirements made of the development and provision of memory circuits are shaped by the continuous trend toward a higher storage density and toward higher write/read speeds in conjunction with a low energy consumption.
It is evident in the case of the prior art that hitherto innovations have successfully been made to a greater extent in the area of the technology of the memories, but have related less to the basic structure of the known standard memory cell.
In the case of the customary basic structure of the UCP flash memory cells, the contained digital information is retained by charged storage on a floating gate.
Thus, the floating gate of such a memory cell transistor is assigned to a word line via a control gate.
If the level of this signal line is at LOW, the memory transistors are not selected for write and read functions.
If, in the case where selection of the memory transistors is present, the read-out of a selected memory transistor that is occupied by a stored charge representing a HIGH level is implemented, a static read current flows through the channel formed between its drain and its source.
In the other case, upon read-out of a selected memory transistor that is occupied by a stored charge representing a LOW level, the channel is not formed between its drain and its source and no or a very small static read current flows.
In the case of the prior art, the read-out of the respective memory cell is affected at fixed potentials of the source and drain of the memory cell transistor. The source and drain terminals of the memory cell transistors are connected in parallel within a bit column via a respective bit line.
The two bit lines have contact-connections in order that these can be put at the necessary fixed potentials. In contrast to other memory concepts in which source lines of different bit columns can be put at a common potential, this is not possible in the case of the UCP memory concept.
This means that a resulting static read current flows on the respective bit lines. The magnitude of the static read current that occurs represents the logic levels of the memory occupancy.
It can be seen from this that two bit lines (for drain and source) are necessary in the case of the prior art for the read-out of the memory occupancy of the UCP flash memory cells. This cell is, therefore, limited in terms of its minimum dimensions to twice the metal spacing in the direction of the word line.
In order to minimize this restriction of the memory space utilization, the current UCP concepts use exhausted metal design rules in the design and production of small cell sizes.
In addition, the critical situation in the design of the cell is increased if the required contact-connections are realized in order to apply the necessary potentials to the two bit lines.
All this subjects the UCP concept to a competitive disadvantage in comparison with other concepts in the case of very large memories.
Therefore, major endeavors are characterized by aiming to obviate bit lines. Thus, D. Shum et al., in U.S. Pat. No. 6,327,182, which is incorporated herein by reference, have proposed placing the metal layers used for the bit lines one above the other.
However, this method is unsuitable for reducing the cell size since the design rules (DR) for the stacked vias demonstrated there necessitate substantially narrower tolerances than the DR for metal layers lying one next to the other.
Owing to the associated lower yield that is to be expected in this case, this makes it rather unlikely that the space saving would be successful.